FPGA Studio v0.0.28
Run your filter on a real AMD Alveo U55C card, or check your own Verilog with Lattice and Gowin synthesis and place-and-route. Use it from Claude or ChatGPT.
Your algorithm.
On real silicon.
Bring a reference algorithm. Build toward an FPGA implementation you can inspect, test, and iterate on.
230 × 648 pxANNOTATION ON
A defect worth
catching.
Locate the annotated region in an actual production image.
This overlay is ground truth,
not a model prediction.
Turn camera frames into a tested inspection pipeline. Define defect recall, line rate, and latency before building.
Current: source-data review · full detector and board validation pendingWaveforms use the verified input and filter contract. They are not stored FPGA readback traces.
3 recorded inputs · 60 positive launches · 200,600 exact output samples. Input mutation and skipped-launch controls checked.
Component verification · no audio-quality or speedup claim
INPUTRECTIFIEDCaptured photo · manually marked cornersStart with calibrated input, geometry, and a latency budget. Compare every output against its reference.
Current: captured-photo CPU warp · vision hardware validation incompleteDesigned for teams moving algorithms
from software to dedicated hardware.
Start with the job to be done.
Inspection, imaging, and scientific instruments need more than generated code. They need a pipeline that meets a measurable acceptance test.
Keep the algorithm.
Close the hardware loop.
The product goal: less setup and rework between a working reference and an accepted FPGA implementation.
Bring your reference.
Start with your code, representative data, target board, and the constraints that matter.
Build against acceptance.
Compare implementations against a frozen reference, then check the actual board output.
Own the result.
Review editable code, build artifacts, measurements, and the records needed to reproduce the outcome.
Part of your workflow.
Not another chat window.
A run-shaped API for your engineering agent. A clear workspace for your team. Submit inputs, follow events, and inspect the result.
POST /v1/runs { "project_id": "your-project", "bundle_id": "frozen-input-revision", "case_id": "vision-warp" } GET /v1/runs/{id}/events
The public build console on this page queues real on-card runs today.
The full run API below is a design preview.
The result should be inspectable.
Research results have different evidence levels. Each demo keeps its input source, verification scope, and limitations attached.
Back to the visual demo ↗What am I looking at in the visual demo?
A real captured OpenCV sample photo, transformed using manually marked planar corners. The 12 CPU reference frames match the C++ simulation. This is not physical lens calibration or an FPGA readback result. The vision hardware build was stopped before completion; no vision board result is available.
Industrial images come from KolektorSDD2 production captures. The threshold component misses many annotated defects; it is not a validated inspection system.
What is verified on an actual FPGA?
Recorded-audio FIR16: three clips, 20 launches each, 200,600 positive output samples checked against the reference on an AMD U55C. Input mutation and skipped-launch controls were checked. This is a filtering component test, with no audio-quality or CPU speedup claim.
Where does the Neuropixels case stand?
The existing MATLAB/C++/HLS consistency evidence uses synthetic data. The DANDI 000034 excerpt is MEArec simulation. This website does not add a real-acquisition on-card result for the separate Neuropixels lane.
Which real industry workflows inform the product?
R.A.M. industrial inspection and Intuitive Surgical image-warping prototyping are documented vendor user cases. They inform the workload choice; these organizations are not represented as our customers or partners.
Open the current visual receipt
CPU reference preview. Hardware receipt not available.
Verify your signal on real hardware.
Choose a seed for a new input signal and verify it on an Alveo U55C using our fixed FIR-16 bitstream. Every run checks the full integer reference and negative controls. Custom HDL and new bitstream synthesis are not available in this preview.
Build queue
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